FTMSYNC=0, RXDFE=00, DLYACT=0, RTCC=0, BUSREF=000, ADHWT=000, ACTRG=0, ACIC=0, RXDCE=0, CLKOE=0, TXDME=0, RSTPE=0, SWDE=0, NMIE=0
System Options Register 0
| NMIE | NMI Pin Enable 0 (0): PTB4/KBI0_P12/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as PTB4, KBI0_P12, FTM2_CH4, SPI0_MISO or ACMP1_IN2. 1 (1): PTB4/KBI0_P12/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as NMI. |
| RSTPE | RESET Pin Enable 0 (0): PTA5/KBI0_P5/IRQ/TCLK0/RESET pin functions as PTA5/KBI0_P5/IRQ/TCLK0. 1 (1): PTA5/KBI0_P5/IRQ/TCLK0/RESET pin functions as RESET. |
| SWDE | Single Wire Debug Port Pin Enable 0 (0): PTA4/KBI0_P4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/KBI0_P20/RTC_CLKOUT/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, KBI0_P20, RTC_CLKOUT, FTM1_CH0, OR ACMP0_IN2 function. 1 (1): PTA4/KBI0_P4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/KBI0_P20/RTC_CLKOUT/FTM1_CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function. |
| ACTRG | ACMP Trigger FTM2 selection 0 (0): ACMP0 out 1 (1): ACMP1 out |
| RXDFE | UART0 RxD Filter Select 0 (00): RXD0 input signal is connected to UART0 module directly. 1 (01): RXD0 input signal is filtered by ACMP0, then injected to UART0. 2 (10): RXD0 input signal is filtered by ACMP1, then injected to UART0. |
| RTCC | Real-Time Counter Capture 0 (0): RTC overflow is not connected to FTM1 input channel 1. 1 (1): RTC overflow is connected to FTM1 input channel 1. |
| ACIC | Analog Comparator to Input Capture Enable 0 (0): ACMP0 output is not connected to FTM1 input channel 0. 1 (1): ACMP0 output is connected to FTM1 input channel 0. |
| RXDCE | UART0_RX Capture Select 0 (0): UART0_RX input signal is connected to the UART0 module only. 1 (1): UART0_RX input signal is connected to the UART0 module and FTM0 channel 1. |
| FTMSYNC | FTM2 Synchronization Select 0 (0): No synchronization triggered. 1 (1): Generates a PWM synchronization trigger to the FTM2 modules. |
| TXDME | UART0_TX Modulation Select 0 (0): UART0_TX output is connected to pinout directly. 1 (1): UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout. |
| BUSREF | BUS Clock Output select 0 (000): Bus 1 (001): Bus divided by 2 2 (010): Bus divided by 4 3 (011): Bus divided by 8 4 (100): Bus divided by 16 5 (101): Bus divided by 32 6 (110): Bus divided by 64 7 (111): Bus divided by 128 |
| CLKOE | Bus Clock Output Enable 0 (0): Bus clock output is disabled on PTH2. 1 (1): Bus clock output is enabled on PTH2. |
| ADHWT | ADC Hardware Trigger Source 0 (000): RTC overflow as the ADC hardware trigger 1 (001): FTM0 as the ADC hardware trigger 2 (010): FTM2 init trigger with 8-bit programmable counter delay 3 (011): FTM2 match trigger with 8-bit programmable counter delay 4 (100): PIT channel0 overflow as the ADC hardware trigger 5 (101): PIT channel1 overflow as the ADC hardware trigger 6 (110): ACMP0 out as the ADC hardware trigger. 7 (111): ACMP1 out as the ADC hardware trigger |
| DLYACT | FTM2 Trigger Delay Active 0 (0): The delay is inactive. 1 (1): The delay is active. |
| DELAY | FTM2 Trigger Delay |